AEGIS

Ensuring AI Reliability and Longevity Through Hardware and Software Cross-Layer Hardening

Abstract

AEGIS aims to push the boundaries of safe AI deployment by addressing a critical reality: the advanced hardware powering AI is increasingly vulnerable to reliability challenges. High-performance AI hardware requires a larger silicon area, increasing fault probability, while peak performance accelerates device aging. This induces transient faults that alter predictions and permanent faults that require device replacement, escalating maintenance costs (linking to 2019's 53.6 million tons of e-waste) or causing catastrophic mission failures.
By making AI robust against hardware faults during both training and inference, AEGIS ensures stable system behavior.
This efficiently unlocks widespread AI adoption in safety-critical fields currently considered too risky.

Funding: [PRIN / 2026]

AEGIS unites a unique interdisciplinary team of world-leading experts. These partners tackled AI reliability separately at single abstraction layers: UniTN focused on radiation transient faults during inference; PoliTO studied permanent hardware faults; PoliMI defined cross-layer frameworks for system-level mitigation; and UniBO integrated architectural hardening. AEGIS merges this expertise to deliver efficient solutions against both transient and permanent faults.

The teams will integrate their methods into a single, documented, open-source methodological framework, creating a unified analysis and hardening infrastructure for the scientific community rather than a fragmented collection of tools.
AEGIS overcomes current limitations by merging expertise covering all abstraction layers of AI reliability. While existing hardening is heavily biased toward software solutions, like selective replication, checksums, and value clipping, rare hardware protections simply apply high-overhead global ECC. AEGIS will uniquely co-design hardware and software hardening, merging beam experiments, RTL visibility, and software scalability into a unified, efficient solution.
Through this cross-layer methodology, the project targets ambitious goals: Identify the source of 99% of observed errors while reducing RTL fault injection time by two orders of magnitude by focusing on critical design portions. We aim to predict the Failure In Time (FIT) rate within 50% and reduce AI framework qualification time and costs by 70%. With the cross-layer hardening we target to reduce fault-induced mispredictions by at least two orders of magnitude and double the operating lifespan of the AI hardware while limiting overall overhead (area, power, and time) to just 10% while fully preserving fault-free accuracy.
Finally, all designed solutions will be open-sourced, delivering the first adaptive, full-stack AI hardening framework. This will allow end-users to select the hardware protection and software modifications that best match their specific project constraints.

Objectives

AEGIS aims to push the boundaries of artificial intelligence safe and effective deployment by addressing a critical and often-overlooked reality: advanced hardware technologies powering AI across all sectors are increasingly vulnerable to reliability challenges. By making AI systems robust against hardware faults during inference and training, AEGIS will enable their widespread adoption in fields where their use is currently considered too risky. Our cross-layer methodology bridges hardware to software and beam experiments to simulations, maintaining high accuracy via cross-validation checkpoints. The key contribution of AEGIS relies in combining software, hardware, experimental, and simulation expertise to design collaborative techniques that increase device lifetime and fault tolerance while reducing overhead.

Project description

AEGIS overcomes current limitations in AI reliability by merging expertise covering all the abstraction layers of AI reliability. Existing hardening is heavily biased toward software solutions, like selective replication, checksums, and value clipping and rare hardware protections simply impose high-overhead indiscriminately. AEGIS will uniquely co-design hardware and software hardening, merging beam experiments, RTL visibility, and software scalability into a unified, efficient solution. The ambitious action of AEGIS is driven by three main research objectives.

Characterize AI hardware permanent and transient fault models

We enable fast, accurate AI reliability evaluations by extracting representative operations from AI models and identifying critical resources within the case-study RISC-V 144-core Picobello architecture. With Picobello available as 7nm chips and detailed RTL descriptions, AEGIS combines radiation beam experiments on live hardware (neutrons, protons, x-rays) and RTL fault injection to trace fault propagation from hardware to output. We target two KPIs: identifying the source of 99% of observed errors, and reducing RTL fault injection time by two orders of magnitude by focusing on critical design portions. Pilot work proved that restricting RTL injections saves 90% of simulation time while maintaining 80% accuracy. Leveraging Picobello's structural details will improve both efficiency and accuracy.

Identify hardware and software sources for mispredictions

We aim at studying error propagation in AI models by statistically injecting errors during execution. Hardware faults from OBJ1 will be translated into software errors as tensor corruptions. High-level error propagation allows fast evaluation of AI models and to categorize errors as tolerable (correct prediction) or critical (misprediction) tracing back to their hardware origin. We will validate error propagation results with beam experiment data across at least three AI models. We aim to predict the empirical Failure In Time (FIT) rate within 50%. This KPI is supported by pilot study whose precision will be enhanced thanks to the open-source architecture. We aim at reducing AI framework qualification time and costs by 70% (assuming three models are executed on the same device) offering a critical advantage for meeting ISO 26262 and ECSS reliability standards.

Hardware-software cross-layer collaborative fault mitigation solutions

We aim to identify efficient mitigation strategies targeting only critical faults from OBJ2. We will implement cross-layer hardening: for software, we will adapt value clipping, filtering, and algorithm-based fault tolerance (ABFT); for hardware, we will implement selective replication on small, critical resources (such as the scheduler), integrate targeted ECC for specific register subsets, and checkpoints to detect control-flow anomalies. Prior evidence indicates that applying separately hardware or software hardening can reduce error rates by up to one order of magnitude, albeit with a 50% overhead. By co-designing and tuning these hardware and software mechanisms, we aim at: (i) reducing fault-induced mispredictions by at least two orders of magnitude, (ii) doubling the operating lifespan of the AI hardware, and (iii) limiting overall overhead (area, power, and time) to just 10% while fully preserving fault-free accuracy. Finally, all designed solutions will be open-sourced, delivering the first adaptive, full-stack AI hardening framework. This will allow end-users to select the hardware protection and software modifications that best match their specific project constraints.

AEGIS research action is divided into three Work Packages that move across the abstraction stack of AI reliability.

(WP1) Fault characterization has the goal of characterizing the impact of hardware transient and permanent faults on the correctness of AI operations. We uniquely combine radiation beam experiments on live hardware (7nm Silicon) with RTL description fault simulations. The device will execute full AI models and benchmarks while exposed to accelerated particle beams of neutrons (for terrestrial applications), protons (for orbital satellites), and X-rays (for radiation-induced dose). Concurrently, RTL fault injection on Picobello description will ensure clear visibility of fault propagation. Ultimately, combining and cross-validating these simulation results with radiation data will yield a highly accurate and realistic fault model for the effects of hardware faults on executed operations.

(WP2) Error propagation in AI models extrapolates from WP1 the abstraction of the effect of hardware fault, to provide a software visible description as a set of possible tensor corruption. Through a dedicated software error injection tool, we propagate the software visible corruption in modern AI models. Once the error reaches the final output we will categorize the effect based on the impact on prediction. Critical faults, that induce mispredictions, will be marked, tracing back their software and hardware origin. We will compare the error rate predicted with fault injection with the one measured via beam experiments to validate our methodology.

(WP3) Cross-layer hardening exploits the software/hardware analyses performed in WP1 and WP2 to design effective mitigation solutions for AI. We will combine experimental FIT rate with the misprediction probability of fault models to estimate the cost of implementing software solutions (checksum, filters, selective replication) to mitigate hardware fault effect. Concurrently, we will estimate the cost and the effectiveness of protecting the hardware resources of the most critical faults (ECC, replication). The team will then decide the most appropriate combination of hardware and software hardening to mitigate the effect of hardware faults in AI models. As a result, we will provide collaborative, adaptive, modular, open source, hardware and software cross-layer hardening solutions that can be easily implemented by the user based on the project constraints.

Contribution

Our team will primarily focus on the error propagation in AI models (WP2), working on the development of an adapted error simulation framework and the design of innovative and effective solutions for error model extractions. Based on the outcomes and characterization of the most critical faults, we will also contribute to the definition of hardening solutions to mitigate fault effects on the final computation (WP3).

Consortium