Cristiana Bolchini
About me
I am a Professor at the Dipartimento di Elettronica, Informazione e Bioningegneria (DEIB, website) of Politecnico di Milano, where I received a PhD in Automation and Computer Science Engineering in 1997, and a Laurea in Electronic Engineering in 1993.
I am part of the Computing Systems Architecture group and I am interested in methodologies for the design and analysis of computing/embedded systems with a particular focus on dependability aspects (fault modeling, fault mitigation, on-line test, diagnosis, reliability-related analyses) targeting various architectures. Within this research area, I am currently working on adopting the usable/not-usable paradigm in fault detection and management rather than the less flexible and traditional correct/corrupted one, that well suits numerous scenarios, where reliability is important but the application context inherently exhibits a certain degree of approximation or inexactness (e.g., image/audio processing, AI-based applications).
In the recent past, my research interests have also covered a completely different area, the Data, web, and society one, in the same department, focusing earlier on very small database design issues and later on context-awareness in data design and management.
Moreover, I am involved in research for the exploitation of ICT solutions for the development of smart buildings and districts to improve energy efficiency through optimised use of resources and users’ awareness. On this topic, Prof. Giuliana Iannaccone, at the ABC department, and I are collaborating, with a focus on Foresight for Sustainable Smarter Built Environments.
Research on these topics is (has been) funded by the European Commission (FP6, FP7 and Artemis JU programs), the Italian government (PRIN and FIRB programs) and companies and foundations (SIEMENS, CISCO, European Space Agency, Silicon Valley Community Foundation).
I coordinated the FP7 SAVE project (Sep. 2013 - Aug. 2016, web site) and I have been one of the proponents of the EU COST Action MEDIAN (Dec. 2011 - Nov. 2015). Furthermore, I have been involved in a project on ICT for energy efficient buildings, the Zero Energy Buildings in Smart Urban Districts project within the National Technological Cluster "SmartCommunitiesTech" (Jan. 2014 - Dec. 2017), while another one recently finished the SCUOLA project, funded by Regione Lombardia in the Smart Cities and Communities area (Mar. 2014 - Nov. 2015). Finally, I am the recipient of two gifts from the Cisco University Research Program Fund, a corporate advised fund of Silicon Valley Community Foundation (one in Dec. 2012, the second in Oct. 2014), to support my research on functional diagnosis.
I serve (or have served) on various technical program committees, including the ACM/EDAC/IEEE Design Automation Conference, IEEE Design, Automation & Test in Europe Conference, IEEE/ACM Int. Conf. on Computer-Aided Design, IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, IEEE On-Line Test Symposium, IEEE Field Programmable Logic and Applications Conference, Euromicro Conference on Digital System Design, Architectures, Methods and Tools, Special Session on ‘‘Fault Tolerance in Digital System Design’’, HiPEAC Workshop on Design for Reliability and HiPEAC Workshop on Reconfigurable Computing. I contributed to DATE in different roles (Friday Workshops co-chair, Tutorial chair, Track chair for the Test track in 2018-2019), Program Chair for DATE 2020 and General Chair for DATE 2022.
I published more than 150 refereed conference and journal papers on dependability and context-awareness. I am serving as Associate Editor for
ACM Transactions on Embedded Computing Systems (2020-),
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2022-), and
I am part of the Editorial Board of Elsevier's Computer Science Review journal (2021-).
I served as an Associate Editors-in-Chief of the IEEE Transactions on Emerging Topics in Computing (2013-2015). I served as an Associate Editor of the IEEE Transactions on Computers (2007-2012) and a Guest Editor for the same journal, for Springer Journal of Electronic Testing: Theory and Applications, for Elsevier Journal of Systems Architectures, and for Elsevier Microprocessors and Microsystems: Embedded Hardware Design for special sessions on Dependability-related special issues.
I also served on the IEEE Computer Society Publications Board (2019-2020) as a Member at Large.
I am an IEEE Senior Member and a HiPEAC regular member.
At present, I am the Rector's delegate for international relationship with the South East Asia (2017-) and leading Technology Foresight workgroup (website).
For IEEE Council on Electronic Design Automation (a.k.a. CEDA), I served as VP Conferences (2022-2023), VP Finance for terms 2020-2021 and 2018-2019 and I am currently President-Elect 2024-25.
Recently, I served on the following academic responsibilities/services for my institution: member of the Computer Science section board (2013-2019), vice-head of the PhD board in Information Technology for the Computer Science section (2016-2019).
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Recent publications on present research
C. Bolchini, L. Cassano, A. Miele, A. Toschi, "Fast and Accurate Error Simulation for CNNs against Soft Errors," IEEE Trans. Computers, Vol. 72, no. 4, pp. 984-997 (2023) doi
A. Miele, H. Zarate, L. Cassano, C. Bolchini and J. E. Ortiz, "A Runtime Resource Management and Provisioning Middleware for Fog Computing Infrastructures," in ACM Trans. Internet Things, Vol. 3, No. 3, pp. 1–29 (2022) doi
M. Biasielli, C. Bolchini, L. Cassano, A. Mazzeo and A. Miele, "Approximation-based Fault Tolerance in Image Processing Applications," in IEEE Trans. Emerging Topics in Computing, Vol. 10, no. 2, pp. 648–661 (2022) doi
C. Bolchini, G. Boracchi, L. Cassano, A. Miele, D. Stucchi, "Fault Impact Estimation for Lightweight Fault Detection in Image Filtering," IEEE Trans. Computers, Vol. 71, no. 2, pp. 282-295 (2020) doi
M. Biasielli, C. Bolchini, L. Cassano, E. Koyuncu, A. Miele, "A Neural Network Based Fault Management Scheme for Reliable Image Processing," IEEE Trans. Computers Vol. 69, no. 5, pp. 764-776 (2020) doi
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